IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level

This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. The headroom of each disjoint closed cone is evaluated based on its slack and slack sustainability. The notion of slack sustainability in conjunction with an embedding threshold enables closed cones in the critical path to be qualified as watermark hosts if their slacks can be better preserved upon remapping. The watermark is embedded by remapping only qualified disjoint closed cones randomly selected and templates constrained by the signature. This parametric formulation provides a means to capitalize on the headroom of a design to increase the signature length or strengthen the watermark resilience. With the master design, the watermarked design can be authenticated as in nonoblivious media watermarking. Experimental results show that the design can be efficiently marked by our method with low overhead

A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design

Finite state machines (FSMs) are the backbone of sequential circuit design. In this paper, a new FSM watermarking scheme is proposed by making the authorship information a non-redundant property of the FSM. To overcome the vulnerability to state removal attack and minimize the design overhead, the watermark bits are seamlessly interwoven into the outputs of the existing and free transitions of state transition graph (STG). Unlike other transition-based STG watermarking, pseudo input variables have been reduced and made functionally indiscernible by the notion of reserved free literal. The assignment of reserved literals is exploited to minimize the overhead of watermarking and make the watermarked FSM fallible upon removal of any pseudo input variable. A direct and convenient detection scheme is also proposed to allow the watermark on the FSM to be publicly detectable. Experimental results on the watermarked circuits from the ISCAS'89 and IWLS'93 benchmark sets show lower or acceptably low overheads with higher tamper resilience and stronger authorship proof in comparison with related watermarking schemes for sequential functions

Constraint-based watermarking techniques for VLSI IP protection

172 p.With the increase, in the popularity of reusable intellectual property (IP) cores for System-on-a-Chip (SoC), piracy is also on the rise in this new design area. The lure of getting a new product ahead of the competitor at a fraction of, or at no cost, is often too much a temptation to ignore, which results in an increasingly buoyant IP theft. To safeguard the IP owner against piracy and illegal redistribution of the IP cores, constraint-based watermarking has been used as a pivotal technology to protect the copyright of the very large scale integration (VLSI) IPs. In this thesis, a comprehensive framework of constraint-based watermarking techniques has been studied and explored at different design abstraction levels. The goal is to develop robust watermarking chemes and techniques for VLSI IP protection that can facilitate easy detection and tracking of IP misappropriation.DOCTOR OF PHILOSOPHY (EEE

Intellectual property authentication by watermarking scan chain in design-for-testability flow

This paper proposes an intellectual property (IP) protection scheme at the Design-for-Testability (DfT) stage of VLSI design flow. Additional constraints generated by the owner’s digital signature have been imposed on the NP-hard problem of ordering the scan cells to achieve a watermarked solution which minimizes the penalty on power and cost of testing. As only the order of the scan cells is varied, the number of test vectors for the desired fault coverage is not affected. The advantage of this scheme is the ownership legitimacy can be publicly authenticated on-site by IP buyers after the chip has been packaged by loading a specific verification code into the scan chain. We propose to integrate the scan chain watermarking with dynamic watermarking of the IP core to make the design hard-to-attack while the ownership is easy-totrace. The proposed scheme is applied to an optimization instance of scan cell ordering targeting at test power reduction. The results on several MCNC benchmarks show that the watermarking scheme has a very low probability of solution coincidence and hence provides strong proof of authorship.Published versio

Identification of state registers of FSM through full scan by data analytics

Finite-state machine (FSM) is widely used as control unit in most digital designs. Many intellectual property protection and obfuscation techniques leverage on the exponential number of possible states and state transitions of large FSM to secure a physical design with the reason that it is challenging to retrieve the FSM design from its downstream design or physical implementation without knowledge of the design. In this paper, we postulate that this assumption may not be sustainable with big data analytics. We demonstrate by applying a data mining technique to analyze sufficiently large amount of data collected from a full scan design to identify its FSM state registers. An impact metric is introduced to discriminate FSM state registers from other registers. A decision tree algorithm is constructed from the scan data for the regression analysis of the dependency of other registers on a chosen register to deduce its impact. The registers with the greater impact are more likely to be the FSM state registers. The proposed scheme is applied on several complex designs from OpenCores. The experiment results show the feasibility of our scheme in correctly identifying most FSM state registers with a high hit rate for a large majority of the designs.Ministry of Education (MOE)Accepted versionThis work was supported in part by the National Natural Science Foundation of China under Grant 61672182, the Guangdong Natural Science Foundation under Grant 2016A030313662, and in part by the Singapore Ministry of Education Tier 1 Grant MOE2018-T1-001-131 (RG87/18)

Identification of FSM state registers by analytics of scan-dump data

Big data analytics have gained tremendous successes in mining valuable information in various fields. However, its potential to solve complex problems in hardware security has not been adequately tapped. This paper presents a non-invasive approach to identify the state registers of a finite state machine (FSM) in an integrated chip. The state registers of the FSM are mined from the scan-dump data by exploiting the strongly connected property and chronologically correlated state codes of the FSM. The sequence of data scanned out of each scan register is partitioned into non-overlapping strings of high weighted frequencies by a string-matching algorithm. A coherency between a pair of registers is defined and computed based on the partitioned strings. The dimension of the coherency matrix is first reduced by pruning some registers of low influence by a regression analysis. The registers are then clustered to minimize the within-cluster variances based on their coherency values. The proposed scheme is applied to some IP cores from OpenCores. The experimental results show that our scheme can correctly identify the FSM state registers in most designs with high hit rate.Submitted/Accepted versionThis work was supported in part by the National Natural Science Foundation of China under Grant 62174045, in part by the Guangdong Basic and Applied Basic Research Foundation under Grant 2021A1515011862, and in part by the Shenzhen Fundamental Science Research Foundation under Project JCYJ20190806143203510 and Project GXWD20201230155427003-20200824112646001

A new PUF based lock and key solution for secure in-field testing of cryptographic chips

Scan-based side-channel attacks have become a new threat to cryptographic chips. Existing countermeasures require a secret test key to unlock the scan chain before in-field testing is allowed. However, test key disclosure poses tremendous risks to multiple crypto chips that share a common test key. We address this open problem of in-field testing by leveraging physical unclonable function (PUF) to make the derived test key unique to each chip. The PUF’s response is invoked only once and hardened into a one-time programmable pad. The PUF response required by the designer to derive a test key of each crypto chip can only be recovered at the time of locking the scan chains without directly reading it out. The manufacturer can test the chip normally with no test time penalty before the passed chips are locked. The proposed solution is analyzed to be secure against all known scan-based side-channel attacks and the overhead incurred for the added security is negligibly small.Ministry of Education (MOE)Accepted versionThis research was supported in part by the National Natu- ral Science Foundation of China under Grant 61672182, the Guangdong Natural Science Foundation under Grant 2016A030313662 and the Shenzhen Overseas High-Level Talent Innovation Foundation under Grant KQJSCX20160226202510, and in part by the Singapore Ministry of Education Tier 1 Grant MOE2018-T1-001-131 (RG87/18)

GSDME-dependent pyroptosis signaling pathway in diabetic nephropathy

Abstract Diabetic nephropathy (DN) is one of the serious chronic microvascular complications of diabetes, and leads to the increased morbidity and mortality in diabetic patients. Gasdermin E (GSDME)-dependent pyroptosis signaling pathway plays important roles in a variety of physiological and pathological processes. However, its role and mechanism in DN are still unclear. In this study, we established a rat DN model by intraperitoneal injection of streptozotocin (STZ) successfully. Structural and functional disorders in the kidney were exhibited on the 12th week after STZ injection; the expressions of caspase-3 and GSDME at protein level in renal cortex were significantly up-regulated. At the 20th week, GSDME-N increased significantly, accompanied by the upregulation of caspase-1 in renal cortex and the release of mature IL-1β (mIL-1β) in serum. Furthermore, we found the protein levels of GSDME, caspase-3, caspase-1 and IL-1β were all increased in HK2 and HBZY-1 cells under high-glucose conditions. We also found that the expression of GSDME-N significantly decreased when caspase-3 was knockdown. In contrast, knockdown of GSDME has no effect on caspase-3. Interestingly, either caspase-3, caspase-1 or GSDME knockdown reduced the release of mIL-1β. Finally, injection of adeno-associated virus (AAV) 9-shGSDME into the rat kidney reduced kidney damage and renal cell pyroptosis in comparison with wild-type diabetic rats. These results indicated that the activation of caspase-1 induced IL-1β maturation, and the activation of caspase-3 mediated cleavage of GSDME responsible for the formation of plasma membrane pore, followed by cytoplasmic release of mIL-1β. Overall, we identified a pro-pyroptosis role for GSDME in DN, which does provide an important basis for clinical therapeutic studies